SystemVerilog Assertions Without dist
SystemVerilog Assertions (SVA) are a powerful feature for verifying the correctness of your hardware designs. They allow you to express complex design properties in a concise and readable way. The dist operator is commonly used in SVA to specify the distribution of events, but there are situations where you might want to avoid using it. This article explores techniques for writing effective SystemVerilog assertions without relying on the dist operator.
Why Avoid dist?
While dist offers flexibility in specifying event distribution, its use can sometimes lead to less readable and complex assertions. Additionally, dist can have performance implications, particularly when dealing with large sequences. Avoiding dist in these scenarios can improve both readability and performance.
Alternative Techniques:
1. Using Sequence Concatenation:
Instead of using dist to specify the order of events, you can concatenate sequences to create a more explicit representation of the expected behavior. For example, instead of writing:
property p;
dist {a; b; c} |-> d;
endproperty
You can write:
property p;
(a ##1 b ##1 c) |-> d;
endproperty
This approach clarifies the exact sequence of events required for the implication to hold.
2. Leveraging the first_match Operator:
The first_match operator allows you to specify the first occurrence of a sequence that satisfies a given condition. This can be a powerful alternative to dist when dealing with complex scenarios where the order of events is not strictly defined.
property p;
first_match {a ##1 b |-> c} |-> d;
endproperty
This assertion checks if either the sequence a ##1 b or a ##1 b ##1 b occurs before c, triggering the implication with d.
3. Utilizing unique and strong Operators:
The unique and strong operators can be used to enforce constraints on the number of times a specific event occurs within a sequence. This can help specify desired behavior without relying on dist.
property p;
unique {a; b; c} |-> d;
endproperty
This assertion ensures that the events a, b, and c occur exactly once before d is triggered.
4. Implementing Custom Sequences:
For more complex scenarios, you can define custom sequences to encapsulate the desired behavior. These sequences can then be used within your assertions, simplifying the logic and improving readability.
sequence my_sequence;
a ##1 b ##1 c;
endsequence
property p;
my_sequence |-> d;
endproperty
This example defines a sequence my_sequence that represents the desired order of events. The assertion p then uses this sequence to verify the implication with d.
5. Combining Techniques:
You can combine multiple techniques to achieve the desired assertion logic. For example, you might use sequence concatenation alongside the first_match operator or define custom sequences incorporating unique events.
Examples:
Scenario: Verifying a simple handshake protocol.
Without dist:
property handshake_protocol;
(req ##1 ack) |-> ready;
endproperty
This assertion checks if the request signal (req) is followed by an acknowledgment signal (ack) before the ready signal is asserted.
Scenario: Verifying a bus transaction with multiple data transfers.
Without dist:
property bus_transaction;
unique {
start;
(data ##1 data) |-> transfer;
end;
} |-> complete;
endproperty
This assertion verifies that a start signal (start) is followed by at least two data transfers (data), and finally an end signal (end) before the transaction is marked as complete.
Scenario: Verifying a complex state machine with multiple transitions.
Without dist:
sequence state_transition;
state1 ##1 event1 |-> state2;
state2 ##1 event2 |-> state3;
state3 ##1 event3 |-> state4;
endsequence
property state_machine_verification;
first_match {state_transition} |-> done;
endproperty
This example defines a sequence state_transition that models the expected state transitions. The assertion state_machine_verification then verifies that the sequence state_transition occurs before the done signal is asserted.
Conclusion:
While the dist operator is a powerful tool in SystemVerilog Assertions, it's not always necessary. By leveraging alternative techniques like sequence concatenation, first_match operator, unique and strong operators, and custom sequences, you can write more concise, readable, and performant assertions. Remember to choose the most appropriate technique for your specific verification needs.